//clK系统时钟为50MHZ 先发低位后发高位 先接收地位后接收高位
module uart_tx (input clk,rst_n, UART_CTS,
output reg UART_RTS,
input UART_RXD,
output reg UART_TXD,
output [7:0] led);
reg [3:0]state;
reg [30:0] count;
reg [7:0] data;
assign led= rx_data;
reg [7:0] rx_data;
reg a,b;//reg[3:0] state;
always @ (posedge clk)
begin
if(!rst_n) begin rx_data<=8'h05;count<=0;end
else begin
case (state)
0:begin a<=UART_RXD;b<=a; if(b && !a) state<=1;else state<=0;end
1:if(count==2603) begin if(UART_RXD==0)state<=2;else state<=0;count<=0;end //采集开始位 0电平的中点
else begin state<=1;count<=count+1;end
2:if(count==5208) begin state<=3;count<=0;rx_data[0]<=UART_RXD;end //计数到数据位的中点
else begin state<=2;count<=count+1;end
3:if(count==5208) begin state<=4;count<=0;rx_data[1]<=UART_RXD;end
else begin state<=3;count<=count+1;end
4:if(count==5208) begin state<=5;count<=0;rx_data[2]<=UART_RXD;end
else begin state<=4;count<=count+1;end
5:if(count==5208) begin state<=6;count<=0;rx_data[3]<=UART_RXD;end
else begin state<=5;count<=count+1;end
6:if(count==5208) begin state<=7;count<=0;rx_data[4]<=UART_RXD;end
else begin state<=6;count<=count+1;end
7:if(count==5208) begin state<=8;count<=0;rx_data[5]<=UART_RXD;end
else begin state<=7;count<=count+1;end
8:if(count==5208) begin state<=9;count<=0;rx_data[6]<=UART_RXD;end
else begin state<=8;count<=count+1;end
9:if(count==5208) begin state<=10;count<=0;rx_data[7]<=UART_RXD;end
else begin state<=9;count<=count+1; end
10:if(count==5208) begin state<=11;count<=0;end //采集结束位
else begin state<=10;count<=count+1; end
11:state=0; //回状态一，检测下降沿
default state=0;
endcase
end
end
endmodule
经过测试：可以正常工做------------主要技术点---下降沿的检测-----数据中间采样-----分频计数值的计算
---下降沿检测：a为50MHZ采样时钟采样的当前接收值，b为前一个接收值，------即当前一个接收值为1当前为0时为下降沿---即算法为b & ！a
---分频系数：50MHZ/9600=5208，也就是说明每计数达到5208时就是9600波特率的上升沿---同理计数到2603为9600波特率的下降沿
---数据中间采样：开始时候计数到2603为开始位的中间点，以后计数到5208时为数据采样的中间点
